Review of Server PCB Layout & Schematic – Part 4: PCI Express (PCIE)

November 14, 2018 Robert Feranec

This video is about: Zig-Zag routing, Stitching VIAs, Stub in PINs, Holes in GND under PADS and around VIAs, Port 80 & POST Codes

Project Olympus:
https://www.opencompute.org/wiki/Server/ProjectOlympus

Files – Olympus Intel:
http://files.opencompute.org/oc/public.php?service=files&t=e969672c57d6e17647adea54f2c3e5a7&download

Cadence document:
https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/pcb-design-analysis/pcb-west-2016-new-techniques-address-layout-challenges-high-speed-routing-cp.pdf

100Gbps design guidlines document:
https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an684.pdf

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