In this video, learn how to setup the required timing budget and simulation analysis options before analyzing the topology (part 6 of 10). Topology Explorer System SI allows you to run circuit or channel simulation for a parallel bus system. In this video, you will use Topology Explorer 22.1 to:
Follow along with these demo files: https://www.ema-eda.com/wp-content/uploads/2023/03/SPBS_Part6.zip
4:17
6:45Learn how to make connections between different blocks in a DDR topology and check connectivity to analyze signal integrity with Sigrity.
3:27Learn how to connect blocks in a Serial Link topology and verify connections for signal integrity analysis in Sigrity.
3:45Learn how to build a block-based serial link topology to perform signal integrity analysis with Sigrity.
3:59Learn how to create an RC circuit in PSpice to perform various SPICE simulations.
3:42Learn how to perform signal integrity analysis for a serial link system and analyze results in Sigrity.
4:03Learn how to setup analysis options for signal integrity analysis of a serial link system with Sigrity.
6:09Learn how to perform power-aware signal integrity analysis for DDR4, analyze the simulation results and generate a report with Sigrity.
6:45Learn how to configure a timing budget and simulation analysis options for power-aware DDR analysis with Sigrity.
4:29Learn how to configure the topology for a DDR device to analyze noise due to switching with Sigrity.
5:12Learn how to configure a power-aware DDR topology and analyze return loss results in Sigrity.
