This quick tutorial will provide step-by-step instructions on how to modify net aliases in bulk using OrCAD Capture and Excel to efficiently update net names. In this video, you will learn:
View the full blog and follow along with this tutorial, use the demo files here.
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6:45Learn how to make connections between different blocks in a DDR topology and check connectivity to analyze signal integrity with Sigrity.
3:27Learn how to connect blocks in a Serial Link topology and verify connections for signal integrity analysis in Sigrity.
3:45Learn how to build a block-based serial link topology to perform signal integrity analysis with Sigrity.
3:59Learn how to create an RC circuit in PSpice to perform various SPICE simulations.
3:42Learn how to perform signal integrity analysis for a serial link system and analyze results in Sigrity.
4:03Learn how to setup analysis options for signal integrity analysis of a serial link system with Sigrity.
6:09Learn how to perform power-aware signal integrity analysis for DDR4, analyze the simulation results and generate a report with Sigrity.
6:45Learn how to configure a timing budget and simulation analysis options for power-aware DDR analysis with Sigrity.
4:29Learn how to configure the topology for a DDR device to analyze noise due to switching with Sigrity.
5:12Learn how to configure a power-aware DDR topology and analyze return loss results in Sigrity.
