This tutorial will provide step-by-step instructions on how to use the Label Tune feature in Allegro Productivity Toolbox to automatically adjust text and improve readability on the PCB. In this video, you will learn how to:
To learn more about how the features of Allegro Productivity Toolbox can expedite your PCB designs, view our latest webinar.
0:54Efficiently create the required via shielding in OrCAD to prevent EMI and noise from effecting design performance with Shield Generator in Allegro Productivity Toolbox.
0:49Quickly and efficiently complete PCB layout for circular boards using the Polar Grid functionality in Allegro Productivity Toolbox.
1:00Quickly shield sensitive signals to minimize crosstalk and noise with the Shield Router in Allegro Productivity Toolbox.
0:46Automatically adjust text to improve readability during documentation, manufacturing and testing with Label Tune in the Allegro Productivity Toolbox.
1:03Quickly create oversized masks to adhere to manufacturing requirements and improve yield with the Mask Generator in Allegro Productivity Toolbox.
1:00Easily design and incorporate spiral inductors in RF and power applications with Coil Designer in Allegro Productivity Toolbox.
6:56Learn how to simulate DDR4 and analyze results and compliance to device standards with Sigrity.
3:42Learn how to perform simulation on a DDR4 device and analyze the results in Sigrity.
5:19Learn how to add probes and setup sweep parameters to perform DDR4 analysis in Sigrity.
5:51Learn how to configure simulation parameters and set analysis options for a DDR4 simulation in Sigrity.
3:15Learn how to setup the required timing budget to perform DDR simulation in Sigrity.
5:30Learn how to connect blocks in a simple parallel bus system topology ad verify the connectivity in Topology Explorer in part 5 of this video series.
5:29Learn how to assign IBIS and S-parameter models to simulate a simple parallel bus system in Topology Explorer in part 4 of this video series.
6:23Learn how to configure a simple parallel bus system topology for analysis in Topology Explorer in part 3 of this video series.
2:38Learn how to model a simple parallel bus system and add blocks to topologies in part 2 of this video series.
2:09Learn how to model a simple Parallel Bus System in Sigrity Topology Explorer in part 1 of this video series.
0:56The Test Point Back Annotation App in OrCAD Capture allows you to efficiently add test points to the schematic that were incorporated during the PCB layout.
3:55This tutorial will teach you how to perform crosstalk analysis for PCIe5 devices and verify compliance with Compliance Kits in Sigrity.
5:07This tutorial video will teach you how to to use Compliance Kits in Sigrity to perform SerDes analysis and ensure compliance of PCIe5 devices.
6:11This tutorial video will teach you how to use Compliance Kits in Sigrity to quickly verify PCIe4 Compliance with a pass/fail report.
