For an accurate analysis of DDR4, it is very important to incorporate the Power Delivery Network into the simulation and analyze the effect of noise due to switching of the parallel bus signal groups.
Part 5 of 5 in this video series will teach you how to run a time domain circuit simulation of DDR4 power-aware parallel bus system, analyze the simulation, and generate a report.
Follow along with these demo files: https://www.ema-eda.com/wp-content/uploads/2023/05/2023PAPBS_Part5.zip
4:17
6:45Learn how to make connections between different blocks in a DDR topology and check connectivity to analyze signal integrity with Sigrity.
3:27Learn how to connect blocks in a Serial Link topology and verify connections for signal integrity analysis in Sigrity.
3:45Learn how to build a block-based serial link topology to perform signal integrity analysis with Sigrity.
3:59Learn how to create an RC circuit in PSpice to perform various SPICE simulations.
3:42Learn how to perform signal integrity analysis for a serial link system and analyze results in Sigrity.
4:03Learn how to setup analysis options for signal integrity analysis of a serial link system with Sigrity.
6:45Learn how to configure a timing budget and simulation analysis options for power-aware DDR analysis with Sigrity.
4:29Learn how to configure the topology for a DDR device to analyze noise due to switching with Sigrity.
5:12Learn how to configure a power-aware DDR topology and analyze return loss results in Sigrity.
