This video will continue to setup timing budget and analysis options for DDR4 SPBS (part 8 of 10). Sigrity Topology Explorer allows you to run circuit or channel simulation for a parallel bus system. In this video, we will use Topology Explorer 22.1 to:
Follow along with these demo files: https://www.ema-eda.com/wp-content/uploads/2023/03/SPBS_Part8.zip
3:59Learn how to create an RC circuit in PSpice to perform various SPICE simulations.
3:42Learn how to perform signal integrity analysis for a serial link system and analyze results in Sigrity.
4:03Learn how to setup analysis options for signal integrity analysis of a serial link system with Sigrity.
6:45Learn how to configure a timing budget and simulation analysis options for power-aware DDR analysis with Sigrity.
4:29Learn how to configure the topology for a DDR device to analyze noise due to switching with Sigrity.
5:12Learn how to configure a power-aware DDR topology and analyze return loss results in Sigrity.
DDR4 and DDR5 complexities require that DDR compliance challenges are understood, and solved with a robust PCB layout and signal integrity analysis.
0:54Efficiently create the required via shielding in OrCAD to prevent EMI and noise from effecting design performance with Shield Generator in Allegro Productivity Toolbox.
1:00Quickly shield sensitive signals to minimize crosstalk and noise with the Shield Router in Allegro Productivity Toolbox.
6:56Learn how to simulate DDR4 and analyze results and compliance to device standards with Sigrity.
3:42Learn how to perform simulation on a DDR4 device and analyze the results in Sigrity.
5:51Learn how to configure simulation parameters and set analysis options for a DDR4 simulation in Sigrity.
3:15Learn how to setup the required timing budget to perform DDR simulation in Sigrity.
5:30Learn how to connect blocks in a simple parallel bus system topology ad verify the connectivity in Topology Explorer in part 5 of this video series.
5:29Learn how to assign IBIS and S-parameter models to simulate a simple parallel bus system in Topology Explorer in part 4 of this video series.
6:23Learn how to configure a simple parallel bus system topology for analysis in Topology Explorer in part 3 of this video series.
2:38Learn how to model a simple parallel bus system and add blocks to topologies in part 2 of this video series.
2:09Learn how to model a simple Parallel Bus System in Sigrity Topology Explorer in part 1 of this video series.
