This video will continue to setup timing budget and analysis options for DDR4 SPBS (part 8 of 10). Sigrity Topology Explorer allows you to run circuit or channel simulation for a parallel bus system. In this video, we will use Topology Explorer 22.1 to:
- Add voltage and current probe points on DQ signals at different nodes
- Setup sweep parameters for Propagation delay
Follow along with these demo files: https://www.ema-eda.com/wp-content/uploads/2023/03/SPBS_Part8.zip