The Case for Stitching Vias on Your PCB

August 20, 2018 John Burkhert

“Circle the wagons.” We can find wisdom in these Pilgrim words. The majority of multi-layer printed circuit boards feature at least one, and often a few or several layers that are a ground pour. The boards with multiple ground planes are interesting since the additional layers imply additional product features. These feature-rich assemblies are often a mix of digital and analog circuits. This is a natural outcome from product specifications in the modern world.

 

The thing is that analog and digital do not play well together without some wizardry from both camps. Coexistence is the science of putting circuits together when they would rather be separated by a lot of space. The product footprint diminishes. The workstation becomes a laptop, which morphs into a tablet, which shrinks down to a phone, then a watch. What’s next? A lapel button? At each node, the challenges grow for the spectrum management and thermal dissipation teams.

Full Ground Planes

Getting back to the ground planes, the copper is the same shape as the circuit board but pulled back from board outline by one or two-hundredths of an inch. The people who calculate the undesirable radiation have a rule that helps keep these spurious emissions in check. It is called the 3H rule. You may already be familiar with an implementation of this rule. 3H stands for three times the dielectric thickness or Height in the Z-axis from the signal layer to the nearest reference ground plane. The variable is used as an air-gap between controlled impedance lines and other copper features on the routing layer.

 

For instance, if the stack-up uses a 5 mil dielectric thickness, then the air-gap rule between the aggressor and victim will be 15 mils. The 3H rule can also be applied to the copper pullback on your power plane layer(s). This would be in addition to the mandated pullback for all copper layers. If the ground pour is offset 20 mils from the edge and the dielectric material is the same 5 mils, we have a total of 20+(3x5) for 35 mils from the edge of the board to the edge of an inner-layer plane or signal trace. (Sorry for the math.)

 


Image credit: Author - the three mil (.076 mm) dielectrics would call for an additional 15 mil pullback on the power planes for EMI suppression thicker layers want more.

 

That is a Pretty Big Pullback

 

It also leaves the outer edges of the printed circuit board with nothing but ground shapes as everything else has a wider keep-in from the edges. Perfect. Now, we can put ground stitching vias all the way around the board. All of the ground planes are locked together into a Faraday cage that cuts down on those harmonics that plague our FCC compliance efforts. The edge of the board is one of those places where it is easy to overlook potential problems. Stringing the vias around the outside while doing the other basics of tooling holes, fiducials, and so on make it a much more natural process than trying to shoehorn the vias in at the end.

 

This same plan is useful for isolating memory busses and staking the frontiers of the analog section(s) or anything with the word “Sensor” in the part description. They say that good fences make good neighbors. Ground planes remain at ground potential when they are well connected to one another. The vias are the nails in the fence. Defining the edges with vias helps prevent the irregularities of the shape from turning into an antenna. All this to say don’t be shy with the ground vias. They keep things cool and quiet when the components get too close for comfort. If you like it, you better put a ring (of vias) on it.

 


Image credit: Author - Note the row of green ground vias around the bus.

How Close is Close Enough?

 

Via to via spacing for EMI suppression depends on the frequency or bitrate of the signals and how much isolation is required. This handy chart shows the wavelengths that we want to corral. The most insane isolation spec I ever endured was 100 dB over a range of frequencies. Picture if you will, that beach that is continuously crop-dusted by passenger airlines. If you had 100 dB isolation, you could hear the waves lapping while your hat takes its own flight from the jet-wash.

 

Scaling this back down to the board level, our Faraday cages around the transmission lines had stitching micro-vias as closely spaced as any fabricator would agree to build. I’d start a second row of ground vias around the traces if there was room. The second row fills in the gaps of the first row. That interstitial method is overkill for most things although some upcoming 5G applications[1]  are bound to call for that sort of isolation.


Image credit; Author - Same area with a power plane shown plus a second row of vias.

The humble ground via is an essential tool for EMI suppression, thermal management and, of course, providing a return path for the signals. Unless you go bonkers, they don’t cost anything extra except for when they perforate other planes. That would be too much of a good thing. Judicious use of vias will make a measurable difference in the reliability of products as the form factor trends to ever smaller outlines. Drill, baby, drill.


References:

https://physics.stackexchange.com/questions/199472/what-is-the-meaning-of-x-db-of-isolation-for-faraday-cage-box

 

http://www.hottconsultants.com/techtips/freq-wavelength.html

 

https://medium.com/supplyframe-hardware/confessions-of-a-pcb-designer-anatomy-of-a-via-f1d6aec236ec

 

 

 

 

 

 


 

 

 

 

 

 


link to 4G/LTE blog once published

About the Author

John Burkhert

John Burkhert Jr is a career PCB Designer experienced in Military, Telecom, Consumer Hardware and lately, the Automotive industry. Originally, an RF specialist -- compelled to flip the bit now and then to fill the need for high-speed digital design. John enjoys playing bass and racing bikes when he's not writing about or performing PCB layout. You can find John on LinkedIn.

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