In-Design Analysis - Sigrity ERC

May 21, 2018 Chris Banton

Problem – Keeping interconnected signals clean and maintaining operating margins is more difficult with smaller, more compact boards. ‘Dirty’ signals reduce performance.

Alternative – Build a prototype and manually check test points and signals with oscilloscopes, digital analyzers and other diagnostic tools. But prototypes are expensive. You could engage an SI expert, but that will add another loop in the process that can create more late-stage changes.

Solution –The PCB designer can easily and quickly identify signal quality issues and causes without the need for simulation models or extensive signal integrity expertise.

Key Points

  • Easy for the PCB designer to use. Visual feedback to identify signal quality issues and causes.
  • Integrated. No import/export. Cross probing. Make a change, and validate the results.

Powerful. Build on Sigrity. ERC & SRC

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