Security Test

Introduction Worst Case Circuit Analysis ("WCCA") is a cost-effective means of screening a design to verify with a high degree of confidence that potential defects and deficiencies are identified and elimi- nated prior to test, production, and delivery and that the design will function, within specifications, throughout its lifetime. It is a critical assessment for high reliability or high production volume systems. The worst case SSO noise analysis portion of the WCCA analyzes the performance of the Power Distribution Network ("PDN") under various load conditions created by the FPGA operation. AEi Systems designed and constructed a specialized 16 layer test board for the RTAX2000 FPGA allowing the FPGA's SSO noise performance to be measured. The SSO noise test data and the PDN model are taken into account in an overall SSO noise PSpice model. The model can be used to predict the pseudo worst case SSO noise performance for the RTAX2000. In order to perform worst case SSO analysis, it is necessary to extract the PCB plane model in order to construct a complete and valid PDN model. An extensive evaluation of various power integrity tools was performed in order determine which tool(s) could accurately predict the PDN impedance. Sigrity's PowerSI provided the closest correlation to the actual measurement for the RTAX board example. Worst Case SSO Noise Example A portion of an actual analysis is shown below as an example of the worst case SSO noise analysis of a FPGA interface (Figure 1). This design includes a RS232 interface, a UART interface that reads configuration data into a large shift register, and the Actel RTAX2000 FPGA. The following data was recorded during temperature and voltage testing: 1. The worst case number of SSOs on each bank. 2. The worst case VDD droop of each bank. 3. The worst case ground bounce of each bank. 4. The boards power plane impedance The SSO effects for standard parts are assumed to be assessed by the manufacturer and already accounted for in datasheet parameters such as output levels or input thresholds. FPGAs have a very large number of SSOs, specific performance requirements, and are produced in small dense packages with complex power distribution networks providing their power. In addition, such ICs have, or could have, very fast output drivers whose current demands place additional requirements on the input PDN. The PowerSI tool is very user friendly. For the purpose of the SSO analysis, the PowerSI Model Extraction simulation is used to extract the PDN information. Figure 1: Top view of the test board populated with RTAX2000 FPGA CGA624 analyzed in this example. Simultaneous Switching Output noise ("SSO") analysis computes the performance of the PDN under load conditions created by the FPGA outputs. In this article, the Sigrity Pow- erSI software is used to extract the PCB plane model in order to construct a complete PDN model. The SSO noise (Vdd droopand ground bounce) is then simulated using PSpice. Sigrity PowerSI Tackles SSO Noise Streamlining the creation of high-speed interconnect on digital PCBs and IC packages

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