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Sigrity PowerSI SSO Noise_2

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Figure 2: Sigrity PowerSI PDN impedance curve shown in PowerSI workplace window (left). The X axis is log scales and Y axis is in ohms. Lab measurement for the PDN impedance curve of the design (right) using the Keysight E5071C. The X axis is log scales and Y axis is in dB ohm. Figure 4: The pseudo worst case SSO noise as computed using a PSpice transient simulation result. This PSpice simulation shows the 23mV VDD droop and 5mV ground bounce for one SSO. ©2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, OrCAD, and PSpice are registered trademarks and the OrCAD logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners. 2327 04 /14 SA / DM / PDF www.orcad.com Sigrity PowerSI Tackles SSO Noise By using specialized parameter extraction techniques, the complete (internal FPGA and external board) PDN model can be constructed and mated with a PSpice model of the driver. The results of SSO simulation can show if the FPGA produces noise that is within acceptable limits under the nominal and worst case conditions. Shown below is the PowerSI simulation for the 3.3V supply plane along with the test measurement. The PDN impedance curve of the actual board is also measured by using the Keysight E5071C network analyzer in the lab as shown below. Both simulation and measuerement plots in Figure 3 are plotted in dB and measured with the same ports, (SMA connector). These ports are connected to 3.3 V supply plane. This design includes two layers of 3.3V supply plane. To compare these two plots, two points has been selected. Impedance at 100MHz frequency for the simulation, Figure 3, is 0.2 Ohms and for the measurement, Figure 4, is 0.2 Ohm. At 1GHz, the impedance for the simulation is 2 Ohms and for the measurement is 1.48 ohms. These results indicate good correlation between the PowerSI simulation and the lab PDN measurement. The differences are largely due to noise and calibration issues. The Vdd droop and ground bounce are then simulated using a PSpice model created by AEi Systems which combines the PDN model with the IBIS driver model that has been converted to PSpice syntax. To characterize the SSO noise, the entire power distribution network has to be considered. It is important to characterize the SSO noise on FPGA outputs at the PCB resonant frequency(ies). There are four main parts to the PDN model: VRM, BOARD PDN, PACKAGE, INTERNAL PDN & CURRENT MODEL OF DRIVER. As shown in this article, the PowerSI simulation, impedance curve simulation, has very good correlation with lab PDN measurement. The report option under the simulation tab gives a summary of the entire project, which saves time when it comes to writing reports. The SSO noise impact (VDD droop, ground bounce noise) occurs sporadically and it is based on the data pattern (software). So, it may not be discovered by functional or qualification testing. If the FPGA output noise is not managed properly, it can cause corruption of data, incorrect operation, and loss of control and software crashes. Therefore, this analysis is highly recommended. The performance of these types of analyses creates many 'lessons learned' for designers. Not only are current designs improved but WCCA supports CIPs (Continuous Improvement Plans) resulting in better future products and better engineers. If you have any question regarding to this article, please contact AEi Systems via email, info@aeng.com, or by phone at (310) 216-1144.

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