The Hitchhiker's Guide to PCB Design

The Hitchhiker's Guide to PCB Design

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78 F F Nets can be grouped into classes for organizational purposes. Assign trace width values to all nets. F F Select a via size based upon estimated design density to allow the largest, practical via pad diameter. Always speak with the PCB supplier to verify the via-to-pad diameter ratio allows enough annular ring to over-drill prior to plating. F F Via size and technology requirements need to be considered at the beginning of a layout. Make sure the aspect ratio of via-diameter-to-PCB-thickness is manufacturable. Allow enough pad diameter to form a sufficient annular ring around the drilled hole. Consider the supplier's achievable aspect ratio of PCB thickness-to-via-size when defining vias. F F On multi-layer designs, perform a via fanout operation manually or automatically to reserve multi-layer interconnection points for each pin prior to routing. Audit for via size, placement, and test point assignability. F F Utilize solid copper layers to form power planes which can also be utilized for EMI shielding and heat sinking. F F Use copper pouring to widen connectivity in smaller, localized circuit areas to increase current-carrying capacity and lower inductance. F F Route remaining power connections after establishing part placement and power plane definition. Base power line width upon copper thickness and proven current-carrying capacity calculations in IPC-2221. F F Select routing line sizes which can be easily manufactured by the supplier. F F Route all critical signals to establish the shortest path with the fewest possible vias while maintaining adjacent proximity to a solid plane return path. F F Consider impedance requirements during setup and adjust line widths based upon calculations from a simple impedance calculator. Remember, the designer's job is just to get close. The PCB supplier will dial in the impedance by adjusting three variables if you allow them to: Trace width, dielectric constant of the material, and distance of trace to reference plane. F F 'Freeze' or 'lock' the critical nets so they will not be affected by push & shove routines as the remainder of the routing is completed. F F Follow a routing order which allows via fanout first, routing of power second, and attention to remaining signal routing third. F F Review routing to check for circuitous route paths which may be optimized. Always check for signal lines crossing splits from an adjacent power plane and mitigate. F F Once routing is complete, perform signal integrity checks and adjust as required.

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