Tutorial: Real-Time Placement Analysis

Team EMA

With designs increasing in complexity and speed, it is more important than ever to ensure your design functions properly. For some device signals, this means ensuring timing of your components. Typically, this involves performing a post-route Design Rule Check (DRC) and adjusting your design accordingly. Issues found in this post-route DRC can require a change in component placement, resulting in additional time and resources correcting the design. With Real-Time Placement Analysis in OrCAD PCB Designer, you can analyze your design, optimize placement and solve timing delay issues BEFORE routing.  This tutorial will show you how to set-up and use Placement Vision in your design to ensure timing of your components. If you would like to follow along, you can download the design files here.

 

Step 1: Open your design in OrCAD PCB Designer Professional and select SetupàConstraints from the toolbar.

Under the Electrical Tab set the necessary constraints to ensure timing of your components.

Note: The following constraints are used in the Real-Time Placement Analysis:
  • Min/Max Propagation Delay: Specifies the minimum and maximum delay requirements for a pin pair.
  • Total Etch Length: Specifies the minimum and maximum etch requirements for a net.
  • Relative Propagation Delay: Specifies the matching or relative delay requirements for a group of pin pairs.
     

 


 

Step 2: Place the components in your design.

Select Place > Quickplace from the toolbar. Select “Place all Components” and Click Place.

Note: The Quickplace window will inform you of the progress and notify you when the Quickplace has been completed successfully.
 

Once the placement has been completed successfully, Click Ok.
 



 

Step 3: Open Placement Vision by selecting Displayà Vision Manager from the toolbar.

In the Vision Manager window, select Placement Vision from the pull-down menu.
 



 

Step 4: Set up the Placement Vision Window.

Set the colors for Fail, Pass and XNetRat by clicking on the color square and selecting the desired color or use the default color settings.

Select Design.

Note: You also have the option to select Current View.
 

Select Ratsnest Timing. This option analyzes the rats for which timing constraints are defined and highlights the Ratsnest in the specified colors.

Note: You also have the option to enable XNet Vision. This will display all the XNet rats in the design. XNets are displayed even if the discrete components are not placed between the driver and receiver pins of the nets. The purpose of this vision is to reduce the ratsnest clutter so the designer can focus on the placement of active components.
 



 

Step 5: Select DisplayàShow Ratsà Of Selection.

This will allow Placement Vision to display the color-coded nets of the selected component.
 



 

Step 6: Click on a component with timing constraints and move it onto the board.

The nets with defined timing constraints will be highlighted. Rotate and move the component until all nets Pass (Highlighted in green if you are using the default colors).

Note: Select the “Placementedit” button or select Setupà Application ModeàPlacementedit from the toolbar to easily place components on your board.
 

 



 

Step 7: Finish placing the components with associated timing constraints and continue your design process.

 

OrCAD PCB Designer Professional uses constraints defined for propagation delay, total etch length, and relative propagation delay to provide a color-coded visual of your component placement. Utilizing this feature in the component placement phase of your design, instead of performing a post-route design rule check of constraints, will reduce time and resources spent on design changes and re-spins. Using Real-Time Placement Analysis in your design will optimize placement of your components and ensure the required timing can be achieved.

Video Tutorial

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