Quick Tutorial: Real-Time Routing Analysis

Team EMA


 

Design Rule Checks are usually performed to identify and resolve any features that may be troublesome for your design, including signal quality and manufacturing issues. Performing these checks AFTER your design is completed can lead to design re-spins or re-routing specific portions of your design. Easily find route quality issues during the routing process with Real-Time Routing Analysis in OrCAD PCB Designer Professional.  This tutorial will show you how to use the user-configurable checks to find and resolve issues in your design in real-time, improving performance and optimizing your design. If you would like to follow along with this tutorial,you can download the design files here.
 

Step 1: Open your design in OrCAD PCB Designer Professional and open the Vision Manager by selecting Display --> Vision Manage from the menu.

Select Routing Vision from the drop-down menu.
 


 

Step 2: Set up the Route Vision Manager.

Set the Color for non-optimized traces by clicking on the color square and selecting the desired color or use the default settings.
Select “Dynamic Log” and “Log Current View Only”.
 

Note: This will bring up the Vision Report Window, which can be docked to the bottom or side of your screen and displays the following information:
  • Item
  • Layer
  • Net
  • Seg/Arc
  • Location
     

You can activate this view by selecting “View Log” in the Route Vision Manager at any time.
 


 

Step 3: Configure the Route Vision Manager. Click Configure.
 

Note: This will open the Route Vision Configure Window where you can select options to check, in real-time, throughout the routing process. For more information on the Route Vision Options, check out the note at the end of this blog post.
 

1. Select the following options from the Route Vision Configure Window and Click Ok:

  • Parallel Gap Less Than Preferred
  • Non-Optimized Segs
  • Non-Ideal Pad Entry
     


 

2. In the Route Vision Manager, set the following values:

  • Parallel Gap Less Than Preferred: 15.00
  • Non-Optimized Segs: 50.00
     
Note: To set the Non-Optimized Segments value, click on “Channel” and set value for Channel Air Gap.
 


 

Step 4: Route your design to review “Non-Optimized Segments”. Select Routeà Connect from the menu.


1. Route the connection between vias for net A4_ADC_GPIO. Right click and select Done.
 

Note: These vias are highlighted in orange and located at coordinates (310.000 2470.000) and (540.000 2510.000).
 


 

2. Delete the previously routed trace by selecting the trace and clicking the “Delete” button on the toolbar.
3. Select Route  --> Connect from the menu. Under the Options tab, click “Optimize in Channel”.
4. Re-Route the connections between the vias for net A4_ADC_GPIO.
 

Note: The color of the trace is no longer highlighted in the specified color as the trace is centered between the pins and vias in the design.
 


 

Step 5: Route your design to review “Non-Ideal Pad Entry”. Select Routeà Connect from the menu.

1. Begin to route the trace for net A1_MUX. Right click and select Done.


Note: This via is highlighted in orange and located at the coordinate (490.000 2420.000). You do not need to fully route this trace. We will only focus on the segment entering the pad.
 


 

2. Select Route  -->  Slide from the toolbar. Adjust the trace until an ideal pad entry is achieved.
 

Note: The segment entering the pad is no longer highlighted in the specified color.
 


 

Step 6: Route your design to review “Parallel Gap Less Than Preferred”. Select Routeà Connect from the menu.
 

1. Begin to route the trace for net A2_MUX. Right Click and select Next.
 

Note: This via is highlighted in orange and located at the coordinate (340.000 2310.000). You do not need to fully route this trace. We will only be looking at the spacing between A2_MUX and A0_MUX.
 

2. Begin to route the trace for net A0_MUX. Right Click and select Done.


Note: This via is highlighted in orange and located at the coordinate (520.000 2300.000). You do not need to fully route this trace. We will only be looking at the spacing between A2_MUX and A0_MUX.
 


 

3. Select Route  --> Slide from the toolbar. Adjust the traces until the desired parallel gap is achieved.
 


 

OrCAD PCB Designer Professional provides real-time, visual feedback for nine common, route-quality issues. Utilizing this feature in the routing phase of your design, instead of performing a post-route design rule check of constraints, will reduce time and resources spent on design changes and re-spins. With real-time routing analysis, you can catch these potential problems during your routing process; optimizing your design and improving signal quality as you go.
 

Note: The following Real-Time Route Vision checks are available.
  • Parallel Gap Less Than Preferred: Specified color is shown for segments with gap less than the user-specified value (value expected to be set larger than the DRC minimum).
  • Non-Optimized Segs: Specified color is shown for non-optimized segments. Optimized traces have a minimum line-to-line spacing and a maximum pad-to-line spacing.
  • Uncoupled Diff-Pair Segs: Specified color is shown for differential pair segments that are uncoupled.
  • Non-Ideal Pad Entry: Specified color is shown for segments having non-ideal pad entry. The first segment outside of the pad must honor the same-net line-to-pad spacing constraint.
  • 90 Degree Corners: Specified color is shown for segments with 90-degree corners (shorter segment is highlighted).
  • Min Miter/Corner Size: Specified color is shown for corner segments having a miter/corner size less than the user-specified value.
  • Min Seg/Arc Length: Specified color is shown for segments whose length is less than the user-specified value.
  • Min Arc Radius: Specified color is shown for arcs whose radius is less than the user-specified value.
  • Non-Arc Corners: Specified color is shown for non-arc’d corners (shorter segment is highlighted). 
     

When configuring Route Vision, OrCAD provides additional information as well as images for further clarification.

Previous Flipbook
10 Common Design for Manufacturing (DFM) Issues and How to Solve Them
10 Common Design for Manufacturing (DFM) Issues and How to Solve Them

Next Flipbook
Achieving PCI-e Compliance: Getting It Right the First Time
Achieving PCI-e Compliance: Getting It Right the First Time

The PCI-e protocol is complex and to meet PCI-e compliance for the electrical category of the Physical Laye...

OrCAD Free Trial

Try OrCAD Today