I still remember a day back in the late ‘80s when an Electrical Engineer invited me into his office and showed me a CAD PCB layout on his monitor. How cool would it be to do that? Well, now I know; pretty cool but frustrating at times as well. Placing and routing are the meat and potatoes of PCB Design. (If you don’t like ‘meat’ then think of your own metaphor.) There are other things to do but this is what holds it all together.
“...time to market is one of the biggest factors in success.”
The basic framework is built around two disciplines, Mechanical and Electrical Engineering. The two main features are the components and, of course, the board. An intelligent set of library parts is essential to getting the placement off to a good start. Over the years, schematic capture has shifted from the PCB Designer’s hands into those of the EE.
Image Credit: Author - The placement of the series resistors was driven by the routing of this memory bus that only used the two outer layers. Note the ground via near every signal via had to be factored in.
The schematic and component libraries are often outsourced or created by an in-house specialist. The goal in the larger outfits is to allow the PCB Designer to focus on placement and routing. Start-ups will put more hats on your head. Either way, our time is a precious commodity not to be wasted.
When and Where to Begin
Jumping right in, We start with a board outline and a netlist, both of which should be considered preliminary. If we were to wait for all of the stars to align before beginning the layout it would be called a waterfall schedule. It’s unrealistic to expect that to happen on a complex layout. Expect some churn along the way. Now, I just mentioned that our time is precious but it is worth it to get in early because it leads to a shorter overall schedule. That is the goal; time to market is one of the biggest factors in success.
Image Credit: Author - Kind of ironic that a board that was supposed to cure a mis-wired flex needed eight blue wires and an exacto-knife in the build kit. We did it all in one day but...
When the goalposts are moved, it can seem like you did a lot of work for nothing. That can be one of the main frustrations. To keep things in perspective, it helps to consider all of the early placement work as a placement study. It’s the same sentiment for routing. You’re finding the pain points and sorting out the power domains. A lot of that work will stick although the neighborhoods may shift around on the map.
“...don’t reinvent the wheel if you can copy a working circuit.”
While you are floorplanning around the critical nets, it is wise to fan-out the chips but to leave the interconnects from chip to chip for later. That makes moving a cluster much easier while retaining the essential geometry for each device. How do you get the “essential geometry”? The first method is design reuse; don’t reinvent the wheel if you can copy a working circuit.
Your Chip Vendor Knows Their Specific Design Requirements Best
Next is the data sheets. Your chip vendors want you to succeed so that you can keep buying their product. They are always eager to show you the best way to implement their chips. Expect them to be conservative with the reference designs and do your best to capture the essence of the data while fitting it into your allocated space. Following the data sheet, if not verbatim then close to it, gives you a backstop when the design review comes and you have to defend your decisions.
“Everyone wants to buy more for less”
You’ll wind up making a lot of decisions with no one looking over your shoulder. Share your work with the cognizant engineer(s) but don’t expect them to be able to see the whole picture while you’re still figuring it out. You’ll build trust by executing the design and they’ll give you even more runway to make mistakes. We have a number of slogans around Microsoft, one of them is “Fail Fast”. Get those mistakes out of the way and make room for improvement. If the mechanical outline shrank while the electrical side grew, consider that an improvement. Everyone wants to buy more for less. You want everyone to be a buyer, right?
Dealing With Uncertainty During the Early Part of the Schedule
Starting at the gnarliest device on the PCB, work your way out leaving a measured amount of slack here and there for both components and routing. I try not to slam everything together at first even if the final iteration will end up that way. There’s too many unknowns; call them unknown unknowns when you don’t even know what you don’t know. Risk management isn’t easy but it is necessary if you don’t want to design yourself into a corner.
Image Credit: Author - Populating only one side of the board and sticking to surface mount components really helps the assembly team.
The Physical Designer can and will need extra clearance for a gusset or a heat pipe. The Electrical Engineer means well when they add another filter cap. Who knew that one of the components was going to become obsolete or come with a 40 week lead-time? The fab shop can and will ask you to upsize the capture pads or add a little more space between the differential pairs. People you didn’t even know were involved could show up at the design review with an agenda that was unknown to anyone but themselves. It happens.
Everyone in the room is under the same schedule pressure with a lot of things on their plate. We’re all in the same boat. I’ve said it before and I’ll say it again, consider any change to be an improvement, never a mistake. Show that attitude and they’ll come back for more. There is no such thing as idle time once you’re on a design. Future proof the layout by making the most of the available area. Un-crowd the components and traces or learn to do so the hard way.
A Word (or Two) About “Social Distancing” on the PCB
Using local vendors requires a different approach than I’d use with overseas fabricators. My snowman pair of vias -- a microvia and a core-via had to be turned into more of a dumbbell than a snowman because I violated the same-net via-to-via rule from the vendor. I had no idea. What worked at Qualcomm way back about ten years (!) ago is no longer good enough. Every core via is met by two microvias. Hundreds and hundreds of them had to be adjusted to add 76 microns of “social distance”.
“There is a lot of value in sending early data to the stakeholders”
That was a rough day and a little more. I was fortunate to have completed the routing study ahead of time. The point is that you need to start with strong design rules and then back off a little more if you can. It was the cumulative space that I left everywhere that made the extra spacing possible without basically starting over. There is a lot of value in sending early data to the stakeholders. Had I not taken the time to generate a DFM document package earlier in the project timeline, the “last minute” would have a long day or two. I’m writing about this ‘improvement’ so that you don’t have to have one of those days.
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