Any PCB stackup will have three jobs to perform: providing power, ground reference planes, and routing channels for your signals. For new designers, one of the questions that repeatedly arises is the layer count required to design a PCB. Without a good grasp of the layer counts required, or how to assign these to different functions (signal, power, ground, or a mix), there is always a risk the PCB does not work properly.
Therefore, in this article, we’ll look at a simple strategy to help designers prepare a PCB stackup based on required layer counts. Determining the layer count is the first step in designing a PCB stackup, especially when designing a digital circuit board with many routing channels and diverse interfaces.
PCB Layer Count Calculation
There are a few simple ways to approach the task of designing a PCB layer stackup. It is first important to identify the type of PCB that will be designed. For example, the PCB could be for a digital system, analog system, or mixed signal. To get an accurate PCB layer count estimate, start with the following process:
- Determine the number of unique routing groups or interfaces
- Determine the number of layers needed to support your largest processor
- Interleave with ground planes
- If the board will a lot of current at high speed, add in at least one power layer
- Round the layer count up to an even number
With this layer count determined, you can move onto other important aspects of a design, such as selecting laminate materials for the signal layers, and the dielectric that separates power and ground planes.
Example With a BGA
Sometimes the easiest way to learn these concepts is to start with an example. Suppose for a moment you want to design a board that includes a 225 pin BGA (15 pins per row/column) with 200 of the pins. As long as the pin pitch is not too small, we can set the layer count by assuming four pin rows per layer. The formula to determine layer count would be:
Signal layers = (0.5 * BGA rows) - 2
In this case, the result is 5.5 signal layers, or rounded up to a total of 6 signal layers just for this BGA.
In this fanout with pitch = 1.0 mm, the outer two rows can support routing on an external layer. Once we get past row 4, we can only support 1 row per layer when through-hole vias are used.
Note that power and ground may take up multiple rows of pins in the interior of the device, which will reduce the number of required signal layers somewhat. Some processors have multiple power and ground pins that will take up multiple rows in the BGA, so the actual signal count for the device can be lower. This brings us to the next portion of the design: power and ground.
Now Add Power and Ground
Next we need to interleave ground between signal layers. For the above example, we would require 5 additional ground layers. Finally, add in one power layer that holds all power rails, and you have settled on a 12 layer PCB.
Now suppose in the above example the power and ground rails occupy two rows in the BGA. In this case, looking at the calculation again, only 5 signal layers would be needed, 4 interleaved ground layers, and 1 power layer are needed. This gets to a 10 layer stackup.
Two Points That Drive Layer Stack Planning
When circuit board densities get high, there are limitations that can require a designer to use more layers in the PCB stackup. Typically this will include:
Smaller Board Dimensions May Add Layers
In some cases, the PCB layout dimensions may be constrained by an enclosure, connector placement, and placement of specific components. It is common to see a situation where the connector placement is defined by the mechanical designer, which then constrains where the PCB layout engineer can place and route other components. Therefore, as the board dimensions get smaller, the number of signal layers tends to increase.
Fabrication Capabilities Can Limit Density
Depending on the density of connections in your board, you might be tempted to place traces close together on signal layers. However, there will be some limit on the density of traces that can be used in a PCB due to a fabrication house’s etching capabilities.
Suppose your fabricator can only reliably etch 4 mil traces. If your substrate material has dielectric constant of Dk = 4, then the required layer thickness for these widths would be 2 mil. Typically the line spacing limit will be set equal to the linewidth, so the density of traces will be set to 8 mil/trace. For differential pairs, the density will be even lower because the linewidth limit may be reached when spacing is about 2x linewidth, therefore your density for differential pairs will be 12 mil/trace.
Don’t Overthink It
The example above involved a large BGA with many pins providing signals, but there are many designs that will not need such high layer counts. One of the most common stackups is a 4-layer PCB. The reason for this is that these PCB stackups can support high speed, high frequency, and mixed-signal, even with reasonably high component density. When signal count gets large too, a 6-layer PCB will be acceptable to use for many products. If you do not need such high layer counts, don’t be afraid of going to lower layer counts.
When it’s time to design your PCB layer stack to support your high-speed signals, use the complete set of PCB layout and routing features in OrCAD from Cadence. OrCAD is the industry’s best PCB design and analysis software with a complete set of PCB project management tools for managing design data. OrCAD users can access a complete set of schematic capture features, mixed-signal simulations in PSpice, and powerful CAD features, and much more.
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