Design rules are nothing new. Our ability to create specific and concrete rules to govern the results should not be overlooked. From the first placement study to the final result, capturing a complete set of rules sets the foundation for iterations and design reuse. Many times, there is no single person who knows all of the design requirements.
Regardless, each functional unit of the team believes that their piece of the action is the most important. Understanding and distilling all of these sometimes competing requirements might provide the most impartial advice on how to proceed with a contentious design. We use constraints as a backstop to avoid anarchy and as a vehicle for design verification. If there are no comparable board files, you have the luxury of starting from scratch and doing it right by design.
Only you can make the rules. That already sounds like a good game plan to me. The ultimate rules of the game are given by Nature. From there onward, it is up to our ability to manipulate matter to our purposes. Over the years, society has grown increasingly complex and with it, our electronics. Every step of the way is paved with advancements, step by step. Can you believe we used to design single-layer PCBs for RF Amplifiers using AutoCAD? We verified the logic by visually comparing the board and the schematic.
Things are different now. There is a netlist. There are symbols that tell you how they want to be connected beyond the graphical information of the schematic. Actually, the symbols know what they want to be connected to but not exactly how. There are usually clues within the net names. Understanding the code and, of course, having shared convention for net naming is the foundation for a good set of constraints. The letters "CLK" should trigger everyone. Groups of nets known as busses are labeled with their general description and a member number.
Net names, the building blocks of design control
It is a fact of life that some other nets that are not quite as obviously labeled might be in a match-group as well. The little segments between the series resistor and the device may have an anonymous system name. The takeaway here is that we have to scrape the data for guidance and context. When you have an interesting chip, something with 80+ pins, for example, it is advisable to skim over the datasheet for any app notes. There could be some strict requirements on this puzzle. During the design, we are quite immersed in the process. The cost of switching over to a new design, even for a short while, is measurable. We grind it out until the tape-out day and move on.
The other half of the job is to capture the design intent.
And that is when the plot twist happens. That day that you were just being helpful rears its altruistic head. Made a few connections to components that weren't really that big but really did need some big copper. The power meter laughs at your skinny trace. Or, maybe it was my skinny trace. I digress. There's a lesson learned either way. It is not enough to capture the design. The other half of the job is to capture the design intent. Design intent includes the obvious items; board outline, connector orientation, keep-out areas as well as the electrical specifications of line length, width, and the air-gap for all the different things.
Image credit: 2krsystems -Typical outline drawing
Placement: Give me some space - but only enough.
We have (or should have) an outline drawing to establish the physical characteristics of the PCB. The rest of the story lives in the Constraint Manager. The more you want the system to do, or verify, for you the more you need the automate the housekeeping duties. ECAD packages have evolved significantly, especially in the area of establishing spacing rules with respect to the function of the individual trace or other geometry. The spacing between the elements is what keeps us safe.
Space, itself, is generally at a premium. Nothing wasted. It would take quite some time to measure the distance between each part and ensure that it meets the list of component-to-component rules. Embedding those rules takes a little bit of Library effort. That effort pays off big time during the placement phase and any other phase that suddenly becomes a mini placement phase.
Capturing the street width between a BGA device and a chip cap in an 0402 package or any other package to package requirement is something a machine can learn. Even better, it can keep track of thousands of interrelationships at the same time. The thoughtful Engineers will ask if the bypass cap is as close as allowed to the power pin. If you have the immediate ability to show her that we're right on the border of too close, you will gain trust a lot more than just saying, "Yeah, we're good" without something to establish the difference between good and overcrowded. I'm serious. There was all of this drama at one company over a component spacing value not meeting the spec. I let it go because I knew that I had built 3 mils of extra headroom into the Constraint Manager. If you wrote the rules, you know how far they can be bent. The auto-router does not.
Let's route smart.
Further, the design intent needs to carry forward as much of the power tree as feasible. From the main line (or lines if your use-case is battery and/or AC) all the way to the little green light, your system's appetite for current needs to be enforced by the hidden hand of Power Integrity. These backroom Engineers have studied all of those datasheets that you get to skim. All of those curves, page after page of graphs are mostly about junction temperatures and signal degradation. All of that sign language gets distilled into your minimum line widths. It's not really as cut and dried as a single width. A short segment that is thinner than the minimum might still pass muster. "Neck-down" regions could be near a connector or where everything comes together in one area. This is one reason that we can have multiple line widths for one net.
Another reason for preset line widths is analog sections. A trace width that provides a 50-Ohm load on the outer surface will not likely meet the requirements when the trace transitions to an inner layer.
Why this is important:
We call it an editor because we spend so much of our time revising existing circuitry. It is not uncommon to route and re-route a connection over and over during the course of a project. The design rules are there for you beyond the width of the copper. When a new trace shoves through a river of existing traces, it is like magic when the other traces politely make way for the new route. It only works if you have your design rules captured. The constraints also make sure your differential pairs remain differential while meeting the phase tolerance.
There is no easy way to tune the lengths of a memory bus without using the electrical rules. The graphical report of your timing budget shows which connections need to be lengthened or shortened. Combined with Auto-Interactive-Delay-Tuning, we make pretty short work of the length matching.
We can also control for crosstalk, number of vias, max length and other attributes under the Electrical tab. Making electrical constraint sets and then assigning those sets to nets as required is a lot easier to manage than assigning constraint “overrides” directly to the nets themselves. Once the groups are assigned, there is a simple way to grab those nets for rat display or to colorize the group(s) or any number of editing functions.
Relax and stay grounded.
With the ground being our favorite neighbor, we have an assortment of different geometries to apply to those special copper pours. A rule set for ground may include different pull-backs for different layers or within certain areas of the board or for a class of nets. You could spend some time crafting the special ground shapes or you could fill in the blanks on the rule set so that the ground pour does what it is supposed to do automatically. The bonus comes when that same information can be portable. Fancy hand-drawn shapes rarely travel well. With ground rules, at least you have a chance of design reuse.
Now apply that thinking to everything else. Do we leave the air-gap around that CLK to chance? Do we randomly route our Random Access Memory? Don't we want the next person who opens this design to have a clue about what is going on? That person could be you in the year 2020. Wouldn't 2020 you have wanted 2018 you to capture what you absorbed while immersed in this labyrinth of copper the first time?
Up above, I mentioned that the rules live in the Constraint Manager. They are alive. They need care and attention or they will end up useless or worse. Future people will do things that make the Design Rule Violations go away. We want those things to be the correct things. Pass on the enlightenment, even if it is only to your future-self.
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