How Ethernet Differential Impedance Influences High-Speed Design

Key Takeaways

  • Contrasting differential signals to single-ended traces.

  • Additional considerations for layout and routing with differential pairs.

  • Design issues that do and don’t necessitate differential pairs.

Ethernet cable and jack

High-speed ethernet design requires special attention to be paid to stackup and impedance

In days past, if you used a telephone that was plugged into the wall you could hear conversations from others bleed into your phone line. Today, high-speed PCB design uses differential pairs to solve these types of signal integrity problems. Not all components will use differential signaling, but differential pairs are the primary routing style used with high-speed digital signaling protocols, including standard computing interfaces like USB and networking interfaces like Ethernet.

The differences between single-ended and differential signals are simple at the physical layout level, but they can be complex at the signal level and in terms of driver/receiver component functions. If you are making the first jump into using differential signaling, this guide will further instruct upon the intricacies of this method. Mastering differential pair routing will provide the foundational knowledge needed to design ethernet differential impedance to promote signal integrity.

What Are Single-Ended and Differential Signals?

Single-ended and differential signaling are two methods for designing PCB traces. Today, digital interfaces are standardized to use one of these methods of signaling: low-speed protocols use single-ended signaling while high-speed protocols use differential signaling, although some low-speed protocols still use differential signaling. These two types of signaling and routing can be used with various topologies.

Single-ended signals are fairly straightforward. The HIGH level is brought up to a logic level (5 V, 3.3 V, etc.) and the LOW level is defined as zero. In differential pairs, each trace in the pair carries the same magnitude, but opposite polarity. At the receiver, the signal is recovered by taking the difference between the signal levels on each line.

 Differential pair voltage

Differential signal recovery at a receiver component

Successful readout and signal recovery requires the lengths of the pairs to be impedance matched within some small tolerance. The advantage here is that common-mode noise will be canceled when reading the signal, as shown in the conceptual diagram above. Ethernet differential impedance matching, like other differential pair length matching, prevents reflections in the lines that undermine power delivery and contribute to poor signal integrity.

Single-Ended and Differential Pair Considerations for Layout and Routing

 

Differential pairs

Single-ended

Impedance

- Characteristic and differential impedance specified.

- Only characteristic impedance is specified.

Length matching

- Required between each trace in a pair.

- Required between multiple pairs on parallel buses.

- Only needed for parallel buses or to match with a source-synchronous clock.

Signal readout

Receiver termination

Parallel termination between pairs (high Z).

Shunt termination to the ground plane (high Z).

Example signaling standards

USB, Ethernet, RS-232, RS-485, HDMI

I2C, SPI, GPIOs

The signal readout and recovery process for differential pairs account for the fact that the two pairs carry equal and opposite polarity signals. This simple idea and parallel routing in a differential pair solve some important signal integrity problems in high-speed PCB design.

Impedance matching (also known as length matching) is a core design aspect of differential signal design. As outlined, the signal recovered at the receiver is intended to be twice the magnitude of either individual trace. However, alternating signals are not static; instead, they fluctuate between peaks and troughs over some period. When arriving at the receiver, the signals must be perfectly out-of-phase to maximize power delivery. Because the arrival time is dependent on the length of the trace travel, the signals must be the same length to achieve this out-of-phase condition at the receiver. Although there is some tolerance in designs as to how much the signal length can diverge, most applications will result in a need to add back the missing length lost on the shorter signal from being on the inside turn. When adding back the missing length, care should be taken to lengthen at the location in the trace where the divergence occurs - the idea being that the more of the distance the traces have in common, the more likely they are going to experience the same local effects of impedance in the plane at that specific area. 

Layout for differential signals does not differ immensely beyond that of a critical single-ended trace. Within reason, component placement should bend to the differential pairs in the case where circuitry may cause EMI issues. Avoid placing power circuitry like switching regulators too close to differential pairs, as the effects of induction will be pronounced. Similarly, routing across split planes should be avoided at all costs due to the extreme EMI issues caused by a circuitous return path.

Ethernet Differential Impedance Applications Offer Routing Solutions

When looking through high-speed signaling standards, differential pair routing is predominantly used. Differential pairs are useful for two major reasons:

  • Common-mode noise - A differential pair is read out as a difference in signal level between the two pairs at a receiver. In other words, any common-mode noise will be subtracted from the receiver and will not interfere with the received signal. This includes common-mode crosstalk that might be received from a single-ended signal.
  • Inconsistent reference - Differential pairs don’t need a uniform ground plane to provide controlled differential impedance. Instead, the pairs reference each other. Interestingly, by calculating the Z-parameters for a differential pair, it becomes apparent that the self-impedance and coupling impedance both diverge to infinity, but the difference between these is a constant.

The image below shows a driver and receiver stage used in low-voltage differential signaling (LVDS). Here, there is no ground plane surrounding the pair. Because the signals have equal magnitude and opposite polarity, the electric field terminates on each side of the differential pair. This particular diagram is nice because it illustrates the situation seen in a standard like Ethernet over UTP cable (e.g., Cat5), which may not have any grounding in a significant portion of the interconnect.

Differential signals driver and receiver diagram

Example differential channel with LVDS

In this example with LVDS, the receiver end is terminated with 100 Ohm impedance, which is equal to the pair’s differential impedance. This eliminates reflection in the differential signal at the receiver end. Because differential receivers have high input impedance, the terminator is placed in parallel with the inputs, converting the injected current into a voltage that can be recovered at the receiver.

What Differential Signals Don’t Solve

It’s important to note that differential pairs are not a cure-all for every signal integrity problem. A differential pair can experience some of the same signal integrity problems as single-ended traces, but they manifest in different ways. Here are the broad signal integrity problems experienced by differential pairs.

  • Differential-mode noise/crosstalk - Contrary to popular belief, differential pairs produce crosstalk and are vulnerable to crosstalk. In particular, differential crosstalk can be induced between two differential pairs, which will then interfere with signal recovery at the receiver.
  • EMI reception - Differential signals can still receive radiated EMI from an external source, but only differential-mode noise will affect the receiver.
  • EMI emission - Differential pairs do emit electromagnetic radiation that can be received as common-mode noise in other interconnects. However, the field polarities from each trace in the pair are opposite, so the emitted radiation is weaker when the pairs are denser.
  • Signal distortion - As a signal travels along an interconnect, it will experience losses and dispersion, both of which will create signal distortion. Differential signals will suffer from signal distortion, just like single-ended signals.

Reference Planes

In both types of signaling, a reference plane near the traces helps solve one problem—it provides shielding against EMI. It also provides a place for some return current around a trace by allowing field lines to terminate into the reference plane. The reference plane also defines the single-ended impedance (characteristic impedance) for each trace in a differential pair as well as in a single-ended signal. Routing tools can enforce length matching in your differential pairs while maintaining controlled impedance during routing.

Designing ethernet differential impedance will involve multiple complementary aspects of PCB design; with Cadence PCB design and analysis software, you can accurately build your project for the challenges of high-speed boards. OrCAD’s advanced routing tools help you follow best practices for layout and routing and you’ll have everything needed to create high-quality designs in a single application.

Leading electronics providers rely on Cadence products to optimize power, space, and energy needs for a wide variety of market applications. If you’re looking to learn more about our innovative solutions, talk to our team of experts or subscribe to our YouTube channel.

About the Author

Cadence PCB solutions is a complete front to back design tool to enable fast and efficient product creation. Cadence enables users accurately shorten design cycles to hand off to manufacturing through modern, IPC-2581 industry standard.

Follow on Linkedin Visit Website More Content by Cadence PCB Solutions
Previous Article
Designing to High Voltage Creepage and Clearance Standards in Circuit Board Layouts
Designing to High Voltage Creepage and Clearance Standards in Circuit Board Layouts

High voltage creepage and clearance design rules arise from safety issues related to arcing between conduct...

Next Article
Component Placement is a Game of Compromises
Component Placement is a Game of Compromises

Notes on why it's important for component placement to meet assembly requirements.

OrCAD Free Trial

Try OrCAD Today