4X Faster Timing Closure on Memory Subsystems with Allegro TimingVision Environment

August 21, 2019 Team EMA

Routing boards with high-speed interfaces had been a time-consuming, manual process at Cavium. To alleviate scheduling pressures without sacrificing quality of their multi-layer boards, the San Jose, CA, semiconductor company automated the process with the Cadence® Allegro® TimingVision environment. In this 3-minute video, Bill Munroe, principal PCB designer in the company's Post-Silicon Group, talks about how the technology helped his team achieve 4X faster timing closure on DDR3 and DDR4 memory subsystems.

No Previous Articles

Next Video
Allegro - Return Path DRC
Allegro - Return Path DRC

Allegro analyzes your design to provide real-time insights and feedback to help you find and avoid potentia...

OrCAD is High-Speed PCB Design Done Right

Get the Free Trial