The following article was originally posted by DeepChip.
CLARITY VS. HFSS WINS PILING UP: And now, in this report, we have EIGHT users validating Clarity is real -- SIX of them with direct data against HFSS. These 9 (total) benchmarks now prove out the Clarity speedup with the same accuracy claims, along with its smaller memory footprint claim. 1. Clarity vs. HFSS Speed-Up "We ran Clarity on up to 24 CPU's -- it was generally 7x faster than Ansys HFSS." "Cadence Clarity had up to a 15X faster turnaround time versus Ansys HFSS ..." 2. Clarity vs. HFSS Accuracy "The accuracy difference between Clarity and HFSS was negligible; no more than 0.5 dB for the full frequency band." 3. Clarity vs. HFSS Memory Footprint "Clarity's memory footprint was only 15 GB. HFSS's footprint was 116 GB -- nearly 8X bigger." MORE CAPACITY == MORE ACCURACY: Users were also excited about the extra capacity Clarity has vs. HFSS -- not just cause they could run more -- it's because they could now run the entire design getting more accuracy. "The largest block we ran on both tools was an 80 mm x 100 mm PCB, with 22 layers and 44 excitations. ... We've always had accuracy concerns with the "cutting" method needed by HFSS to improve runtime. Clarity's higher capacity resolves this." "We can now put our entire design into Clarity for analysis vs. breaking it up. When we break it up for HFSS, we have to make approximations and sacrifice some accuracy. Not with Clarity." - from 6 direct hands-on CDNS Clarity vs. ANSS HFSS user benchmarks
From: [ Quagmire, from Family Guy ] Hi John, Please keep me anonymous. I work at a very large company that builds consumer electronic systems. Our products are used in everything from telecom, to cell phones, to RF and IoT. My team is responsible for design, verification, and signoff of our PCB boards as well as full system package designs. We easily have way, way over 100,000 collective man-hours using tools like HFSS, Sigrity, and SiWave. We are quite comfortable with them and are familiar with the pros and cons. Here's our experience comparing ANSS HFSS to the new CDNS Clarity tool. HOW OUR HFSS FLOW EVOLVED Overall I would say Ansys HFSS is very reliable and gets the job done. It's been the gold standard in our business for decades. But as our designs become more complex, there's a few things trending I've noticed: 1. A significant increase in HFSS analysis run time 2. Increased HW compute resources needed to complete our HFSS analysis. 3. A need to trade-off capacity for performance with HFSS, which affects accuracy The workaround for these HFSS capacity limits in our larger PCB designs is we typically do certain level of "reduction", or "cuts", on the PCB design database so that HFSS is able to run on the hardware server configuration we can grab. There are two ways we can "cut": 1. Cut "unnecessary" signals and geometry patterns; but the risk is we may cut important coupling effects or a signal returning path. 2. "Physically" cut the entire chip/package/PCB system into multiple sub partitions; we cut the system into pieces and then run analysis to compare against results when the system isn't cut. Regardless how we "cut", it heavily depends on a user's experiences from similar designs previously done -- and the final analysis is likely to lose some accuracy.
If a brand-new chip/package/PCB design comes to us the very first time, we have to do a mess of "trial-&-error" iterations to build our confidence until a reasonable "cut" is achieved. (In our practice, we tend to keep more while cutting less because of accuracy, but performance sometimes is a bottleneck in delivering a solution on schedule if large partitions or signals are still in the run. There always seems to be some "magic" that you need to know in order for HFSS to figure out how an EM field behaves.) OUR HFSS VS. CLARITY BENCHMARK Our immediate first question was to see is if Clarity can solve some of the more challenging problem designs that HFSS couldn't. We ran multiple design styles to benchmark accuracy/capacity/performance; but I am only going to single out three as our experiences with Clarity. ---- ---- ---- ---- ---- ---- ---- Testcase #1: Establish Accuracy and Performance First thing we needed to do was establish a Clarity accuracy baseline with our "known good" results. We have several designs to choose from depending on the analysis criteria. For this case we chose a small SERDES block that we have "known good" HFSS results that correlates well to our production system results. This flip-chip BGA core package was 45mm x 45mm with 12 routing layers. ANSS HFSS CDNS Clarity delta ------------- --------------- ----------- Performance: 22 hours 5 min 4 hours 10 mins 5.3X faster Mem footprint: 600 GB 90 GB 85% reduction For servers, both ran on two 32 core machines with 32 CPUs each. For accuracy, we confirmed the Clarity results matched (+/- 1%) our expected HFSS numbers and real life measurement numbers. Side note: it was very easy to setup and run Clarity. We're HFSS users. We only had minimal training from the CDNS AE, then we were able to figure out the Clarity tool on our own. ---- ---- ---- ---- ---- ---- ---- Testcase #2: Can Clarity Analyze An HBM Interposer Design? Many of our products require analysis of advanced packaging like silicon interposers, 3DIC, etc. This particular test case is an HBM interposer. It is challenging due to its large aspect ratio. This test case was: - 0.276mm x 5.288mm (large aspect ratio) - 3 RDL layers - 48 signal nets - 4.6 million mesh elements - 200 ports This design stressed the capacity limits of HFSS. It runs but just takes a very long time if we select many signals to analyze. Often, we find that we need to massage the database by hand to get HFSS to recognize the silicon design database -- meaning we're modifying its layout geometry, merging layers, etc. -- by hand. While hand-tweaking is not terribly complex, it's a time consuming step that can introduce unexpected errors in the FEM analysis. We've sometimes spent a few days checking and double-checking our assumptions for accuracy when a new design comes in just to make sure we're not adding errors to our analysis. Unlike HFSS, most of the time Clarity *usually* understands all those IC layers and runs the raw data out-of-the-box without any modification. However, after importing this HBM interposer design, Clarity *struggled* to generate the initial mesh for analysis. We've seen this in a few cases with Clarity where generating the initial mesh required some manual help from additional cmd options. In this case we had to run a few experiments to find the following cmds: 1. "Equivalent Dielectric" and "Via Clustering" in IC layout 2. "Simplify Polygons" in Edit->Shape 3. "Model Cleanup" function (Keep in mind that this in nothing like the hand modifying of the data that we had to do to get HFSS to work -- this was more about us trying to find the right instructions to feed Clarity to get it to work the best way.) Anyway, once we found them, with these settings we had good starting point and we were able use Clarity's adaptive mesh solver to best effect. ANSS HFSS CDNS Clarity delta --------------- --------------- ----------- Performance: 74 hours 31 min 18 hours 11 mins 4.1X faster Mem footprint: 480 GB 82 GB 83% reduction While we spent several hours experimenting different cmd options to find a good starting point, Clarity overall was still able to produce accurate results ~4x faster than HFSS, and with 17% of the memory. WARNING: While both Clarity and HFSS matched for both ends of the frequency sweep, there was a range in the center where their results differed. But because interposer wires are thin silicon, we can't do physical measurements to see which tool was closer to being right in that divergent range. ---- ---- ---- ---- ---- ---- ---- Testcase #3: Can Clarity Analyze Designs That HFSS Can't? Our last test case is memory module card. It's a complex system of 8 memory pkgs on a single PCB. This is a very challenging design: - PCB + package: 2L flip-chip packages, 4 on top and 4 on bottom - 13.6in x 6.5in - 40 ports - 58 million elements - 12 layer memory module It has a very wide frequency range and must work under several operating conditions. The combo of IC layer stack-up and PCB layout forced us to partition the design data and make approximations to *try* to get it working in HFSS. Even after several tries we've never been able to analyze it in HFSS due to the large amounts of data. In contrast, since Clarity understands all those IC layers and it has the computational capacity, it ran this memory module without any approximation for the package parts as well as the board on: - 4 machines, 32 CPU cores each machine - 8.0 GB of memory per CPU slot with the total analysis time of: 27 hours 53 min Later this Clarity EM analysis was confirmed to be within +/- 1% of the physical measurements of the design. In short, Clarity is the first EM tool we've seen that can analyze/signoff a massive 40 port/58 million element system design like this. ---- ---- ---- ---- ---- ---- ---- We can confirm the "multi-CPU distributed processing" claims that Anirudh makes are real from what we've seen first hand. We're not getting rid of HFSS in our house. We need it for legacy designs plus we have customers who use HFSS, so we have to match them. But for new designs, we are encouraging our engineers to instead use Clarity because it gives them accurate EM results 4x to 5x faster than HFSS while using less compute CPU's and 85% less memory. And over time, we want to see how Anirudh's R&D handles the meshing large 3D structures problem as his Clarity code matures. - [ Quagmire, from Family Guy ] ---- ---- ---- ---- ---- ---- ----