With frequency and data transfer rates increasing, it is crucial to verify adequate power can be delivered to vital components in the design. The inability to supply adequate power in time can result in intermittent board failure and hours troubleshooting in the lab. Addressing loop inductance can help designers reach a design "sweet spot" where inductance is minimized and capacitance is maximized. In this eBook you will learn:
- The effect of loop inductance on the Power Delivery Network (PDN)
- Capacitance rules of thumb
- How to determine, fix, and improve loop inductance