There are two cases where the words annotation and back-annotation will come up in the context of PCB design. One has to do with the general EDA (electronic design automation) workflow: you’re moving from schematic to PCB layout and back again multiple times, and simply need to ensure that all the reference designators are still relevant. The other is a bit more technical and has to do with electronic simulation. There’s a concept called propagation delay. Regardless of which brought you to this post, we’ll cover everything you need to know about annotation and back annotation in PCB design.
What do we mean by annotation and back-annotation in PCB design?
Let’s take a look at your basic EDA workflow.
The PCB design process generally starts with a schematic: a simple block diagram of the different components and their connections. Absent from the schematic are any details of the physical layout of the board. The schematic simply represents the components and their electrical connections. It is essentially a visual manifestation of a netlist. You create the schematic using an EDA tool called a schematic editor (e.g. OrCAD Capture).
The next phase of development is to take that schematic and transform it into a physical board layout. The PCB layout is a 3D representation of schematic, containing all the physical dimensions of your board, including the size of components, traces, holes, and other features. This is handled using an EDA tool called a PCB editor (e.g. OrCAD PCB Editor or Cadence Allegro).
As you’re probably already well aware, one rarely just goes straight from schematic to layout to production. Instead, design is more iterative, with simulation identifying design improvements that generate engineering change orders (ECOs) which require both schematic and layout to undergo numerous updates.
The process of keeping the schematic information up to date with the layout is called annotation. Since changes are often discovered on the layout stage, you’ll often find yourself updating the schematic to match your new layout, updating the data entries for the schematic based on changes to the layout is called back annotation.
Most of this occurs automatically when you use schematic and PCB editors from the same family of EDA tools.
The next question you might ask, is what information is being updated when you annotate a layout or back-annotate a schematic? Recall that a netlist consists of reference designators for components and their corresponding connections. When you have to manually back-annotate a schematic, you are usually renaming a reference designator, changing a pin number, or swapping gates.
Circuit simulation plays a critical role in designing PCBs for manufacture. If you want to gauge how your board will perform in the real world before investing in the physical fabrication of a prototype, electronic simulation is the way to go.
Your most basic circuit simulation will take a netlist of components and connections and run some calculations to model its electrical performance. This test can be run in a schematic editor or on the PCB layout itself.
As you might have guessed, the simulation will be more accurate if run on the layout where propagation delays based on component locations can be factored into the simulation. Two identical components can experience very different logic gate timings depending on where they are physically located in a circuit. As a result, your PCB layout can end up very different from your schematic, necessitating an update.
Both annotation and back-annotation are much easier when you use EDA tools from the same family of software. Often times it’s as simple as extracting data from the layout and loading it into the schematic to ensure all information is correct. Check out Cadence’s suite of PCB design and analysis tools today.
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