So you’ve created a PCB schematic using OrCAD Capture, and you’re ready to take your design to the next step in the electronic design automation (EDA) process with a PCB layout tool. How would you do it?
Well if you’re like most PCB designers, chances are high you looked up a quick 2-minute tutorial video, generated the requisite “netlist” and integrated it into your chosen PCB layout tool, and moved straight to designing.
But if you’re curious as to what exactly a netlist is, and what’s going on behind the scenes when you create that intermediary file, this post is for you.
What is a netlist?
Take a look at your schematic and think for a moment. If you had to manually transfer the most vital information from your schematic into the more comprehensive PCB layout tool, what would be the most efficient way to do it?
You might strip out all the visual elements of a schematic, and just focus on transferring the connections between components. If a net is a connection between two components, a netlist is simply a list of the electrical connections that describe a circuit.
Netlists can vary widely in terms of formats and the amount of information they convey. Here’s an example of the type of information that will be included in a netlist:
Reference designator (e.g. C1 for the first instance of a capacitor)
Signal keywords (e.g. GND)
What follows is a simple example of a netlist produced by OrCAD Capture in PADS-PCB format:
U2.7 C2.2 U3.3 C1.2 U1.5
Netlists are pretty straightforward to read even if you’ve never encountered a particular format before. In NET1 above we can see that C2.2 refers to pin 2 of the second instance of a capacitor which is electrically connected to pin 7 of a part given the generic designator U2.
There will be a parts list preceding the netlist telling you what each designator is referring to, in this case, U2 refers to a dual in-line package.
Document netlist changes
Understanding how to read a netlist will help you troubleshoot errors that occur from using netlists from third-party libraries. Common reasons to modify a netlist include:
Pin number changes
Redundant net names
It is important to document any changes you make to a netlist. If you encounter an error during integration, it’s worth checking whether there are any special character violations, pin number mismatches, or redundant net names that need to be addressed before you can start designing your layout.
Another way to avoid netlist violations is to stick to the same EDA software ecosystem. OrCAD Capture integrates seamlessly with both OrCAD PCB Editor and the more comprehensive Cadence Allegro PCB layout tool. Check out Cadence’s suite of PCB design and analysis tools today.
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