Quick Tutorial: Real-Time Design for Test (DFT)

June 20, 2019 Team EMA

Incorporating testing into your design is critical for the success of your project. By setting Design for Test (DFT) constraints, you can check items such as testpoint spacing or testpoints under components to ensure the testability of your design.  OrCAD PCB Designer Professional uses visual indicators to flag these issues in real-time, saving you time by correcting the design as you go instead of after completion.
 

This tutorial will show you how to use and configure the Design for Test constraints included in OrCAD PCB Designer Professional, to ensure your board can be efficiently manufactured and tested. If you would like to follow along with this tutorial, you can download the design files here.
 

Step 1: Open your design in OrCAD PCB Designer Professional and open the Constraint Manager by selecting Setup→ Constraints from the menu.
 

Select the Manufacturing Tab in the Worksheet Selector section of the Constraint Manager.
 

Expand the “Design for Test” (DFT) tab to view the available constraints.
 

Note: Constraint rules can be created in the “DFT Constraint Set” section and assigned to portions of the board in the “Design” section. For information on all the available Design for Test Constraints, see the final note in this blog post.
 


 

Step 2: Create a Constraint Set (CSet). Select the Mask and Silkscreen Worksheet under “DFT Constraint Set”.
 

Click in the “New CSET” column. Set the following information:

  • DFTMaskCSet: DFT_Mask
  • CSet Usage: Non-Etch


Click OK.
 


 

Set the following information:

  • Testpoint on solder mask: ON
     


 

Step 3: Create a Constraint Set (CSet). Select the Spacing Worksheet under “DFT Constraint Set”.
 

Click in the “New CSET” column. Set the following information:

  • DFTSpacingCSet: DFT_Spacing
  • CSet Usage: Etch
     

Click OK.
 


 

Set the following information:

  • Testpoint under component: ON
     


 

Step 4: Assign the Constraint Set. Select the Mask and Silkscreen Worksheet under “Design”.
 

Right click on “Not in stackup” and select “Add Subclass New”.
 


 

Set the following information:

  • Name: Mask1
  • CSet Ref: DFT_Mask
     

Select the following Film Records:

  • smask-bot
  • smask-top
     

Click OK.
 


 

Step 5: Assign the Constraint Set. Select the Spacing Worksheet under “Design”.
 

In the “Referenced DFT CSet” row, assign the DFT_Spacing Constraint Set to “All”.
 

Note: This will assign the DFT_Spacing Constraint Set to all the testing layers (top and bottom).
 


 

Close out of the Constraint Manager Window.
 

Step 6: View the DRC Errors using the DRC Browser by selecting Tools→ DRC Browser from the menu.
 

Select Design for Test→ Mask and Silkscreen→ Testpoint on Solder Mask.
 

Click on any coordinates under “DRC Location” to be brought to the location of the DRC Error on the PCB.
 


 

Place the curser over the DRC Marker to view more information.
 


 

Step 7: Modify the Design Padstack. Right click on the pad with the DRC Error and select Modify Design Padstack→ All instances.
 

Note: This will bring up the Padstack Editor. If you are having trouble selecting the padstack, in the Find tab uncheck “DRC Errors”.
 


 

Select the “Mask Layers” tab in the Padstack Editor.
 

Set the following value under SOLDERMASK_BOTTOM:

  • Diameter: 20
     


 

Step 8: Update the design. Select File→Update to Design and Exit.
 

Note: If you receive a warning when updating the design, for this purpose of this how-to select “Close” and “Yes”.
 

The DRC Errors have been resolved and the DRC Markers are no longer visible.
 


 

Step 9: Back in the DRC Browser, view the other Design for Test DRC Errors by selecting the following path in the DRC Navigation Tree: Design for Test→ Spacing→ Testpoint under component.
 


 

In the DRC Location Search bar, type in “1782” and click on the filtered coordinate (1782.000, 415.000) to be brought to the location of the DRC Error on the PCB.
 


 

Place the curser over the DRC Marker to view more information.
 

Note: If the DRC Error information is not visible, in the Find Tab check “DRC Errors”.
 


 

Step 10: Move the Testpoint. Click and hold the via.
 

Note: If you are having trouble selecting the via, in the Find tab uncheck “DRC Errors”.
 


 

Slide the via out from under the component.
 

The DRC Error has been resolved and the DRC Marker is no longer visible.
 


 

Note: The following Design for Test Constraints are available:
  • Outline: Checks the minimum distance from the center of a testpoint to the board outline or cutouts.
  • Mask and Silkscreen: Checks the minimum distance from the center of a testpoint to silkscreen and checks missing soldermask.
  • Spacing: Checks the minimum distance for testpoint to: testpoints, components, pins, vias, and non-plated holes. Checks for testpoints under components.
  • Probe: Checks minimum pad size of testpoints.

     

With testing being a vital part of the design process and its success, it is important all aspects of the board can be tested and that the testing results do not reflect manufacturing errors. By utilizing constraints for testing specifications, you can detect and correct any potential issues DURING your design process. Minimize costly design respins by ensuring the manufacturability and testability of your designs with Real-Time Design for Test in OrCAD PCB Designer Professional.

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