Notes from the Board Room: on Signal Integrity

June 7, 2018 John Burkhert

 

 

 

 

Keesight, nee Agilent has me on their mailing list and sends me beautiful pictures

 

Signal Integrity is a make-or-break chunk of the design effort. Let's say that the last little bit of blue space on the board is right next to the RF receive chain. Let's further assume that at the last minute, we decided that the system would have more applications and thus more customers if we could add an external oscillator to the equation. Lucky you, the balls for the XO circuit are pretty close to the open space. It was meant to be, right? Probably not.

 

Rather than place the noisiest part next to the most sensitive line, you're much better off finding a nice big shunt capacitor to swap into that location and then shoe-horn the VCXO device in where the cap was. For sure, you're going to have to put guard-bands around the XO lines and extend your voltage plane to grab the hot pin of the bulk cap. More vias, more rerouting, less time to do whatever you'd rather be doing.

 

 

While this exact scenario will not materialize, bearing in mind the aggressors and the victims during placement will. Painting them as such for the critical net review will show that you know and care. Your payoff will come in the form of those new customers' joyfully sending checks made out to your company.

 

 

While that may not line your pockets, it will feather your nest a lot better than a product that is dead on arrival. By the time you've learned the hard way and generated a re-spin, the fickle customers have flocked to the rock-star team that did it right the first time. Be that Rock Star. Run that new placement past the SI/PI expert. Their advice is rarely easy to implement, but the dividends are real and worth your time.

 

 

Get the Most out of SI/PI

 

You can keep the Signal Integrity team out of the critical path to some extent by doing the things that interest them first. I might do 20% of the placement, just enough to route the DDR and turn it over to them for simulation. While that churns, I'm baking in the differential pairs and any RF signals for round two. If you're going mobile, then the power is probably where much of the drama lies. That's the PI in SI/PI and their advice is beyond golden. Again, it's rarely easy and often counter-intuitive.

 

 

Many times, I've been told that this or that signal is not important. I'm tempted to tell them to remove the unimportant stuff if it's so unimportant. Of course, it is important. It just depends on who you ask. It is a matter of degree though. Un-route your perfectly beautiful and elegantly routed traces and make way for functional improvements. Say "thank you" to the person who just saved your ass.

 

 

The visible output from the SI/PI team is somewhat subtle. It may seem that all they do is take the timing budget from the chip vendor and the impedance rules from the fab vendor and marry the two in the constraint manager. Just like the duck with the calm demeanor, they are paddling like crazy just below the surface. On any project, probably several chips need their attention.

 

 

Take your average 87-page data sheet. There are two or three pages of layout, a footprint and possibly a few app-notes or a sample placement. That leaves 80+ pages, sometimes 800+ pages for the other people. SI's primary concerns are data rates and degradation/radiation. When is the last time you heard an advertisement for a newer, slower product? It's faster every time; faster switching and more of it.

 

 

The Need for Speed

 

 

As we turn up the speed, the little things that could be ignored in the past become more important. An unnecessary via can lead to magnetic coupling, crosstalk, reflections, ground bounce, ringing, overshoot, undershoot, all the buzzwords in one little oversight. The SI team has responsibility for the entire signal chain. Keeping things tidy on the PCB is one of the few places that real improvements can be made.

 

 

Unless you're part of a chip vendor, there isn't much we can do to improve things on a nano-scale. Without owning the connector company, we're pretty much stuck with the discontinuities at the macro level. The SI/PI folks obsess over the PCB layout nearly as much as we do.

 

 

Aside from sharing early and often, we can affect the outcome in a few ways. I mentioned my favorite stack-up in another chapter. You can probably guess what my favorite net is. Hint: It's right below your feet. The ground is everything. It keeps things separate, keeps them cool, keeps them on track and shows them the way home. Every layer should be a ground layer. It's more ecological to flood every layer that isn't already flooded. Ground it for the planet!

 

 

Stay Grounded

 

 

A ground is only as good as the vias that hold it together with the rest of the layers. Most designers know the high-speed rule of adding a ground via wherever the signals transition from one layer to another. In some cases, we take it to another level by creating a coax in the z-axis using a gang of ground vias around the signal via. Anything 2.5G and beyond deserves as much. While you're at it, go ahead and drop some ground vias along the high-speed paths. They're much easier to keep in the layout than to try to put them in after all of the "unimportant" routing has taken place.

 

 

Pro tip: Let's say you're flooding a signal layer. Use a minimum aperture for the copper equal to or slightly greater than the diameter of the via. That way, no copper will pour where you can't support it with a via. An unsupported icicle of ground is an antenna. Air is better. Let the circuit breath.

 

 

Add a little extra clearance like plus one nominal trace-width all around. It will come in handy when you have "just one more thing". If you're already using a 3X line-width rule, that's enough to keep the ground from forming a co-planar structure. Using manufacturing minimums will get you some of those unfortunate things that were attributed to the stray via. Starting with 4X and negotiating down as needed is future proofing against line-width increases. Forcing the isolation on a congested board is never any fun.

 

 

Set a higher than usual threshold for the minimum piece of copper. This will help avoid islands. Anything smaller than six square millimeters isn't helping - except on a phone where every sliver of ground matters. Stake it all down to the proper ground layers above and below the trace layer.

 

 

Final Thoughts

 

 

You can help the SI/PI team help you by at least browsing the other 80 pages of the data sheet. I can't decode a Smith chart or do Math that uses more than a few Greek letters. I can't make much sense out of all of those silly little graphs, but occasionally a nugget of useful information will emerge from the material.

 

 

Eventually, the lingo starts to creep into your cranium. That will come in handy the day you don't have an SI/PI person around. If that's the case now, or even if it isn't, browse on over to SignalIntegrityJournal.com and click on an interesting article or two. There's nothing wrong with having a little more integrity.

 

 

About the Author

John Burkhert

John Burkhert Jr is a career PCB Designer experienced in Military, Telecom, Consumer Hardware and lately, the Automotive industry. Originally, an RF specialist -- compelled to flip the bit now and then to fill the need for high-speed digital design. John enjoys playing bass and racing bikes when he's not writing about or performing PCB layout. You can find John on LinkedIn.

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