Maintaining the rules for tight pin areas can be timing consuming. Manually making changes to tight-pin areas takes up time you could be using to concentrate on more important tasks. OrCAD helps you eliminate the need for manual checks and changes through constraint regions. You define constraints physical and spacing constraints for specific regions and OrCAD automatically follows these constraints when routing.
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Whiteboard Wednesday: Assembly Drawings
The purpose of an assembly drawing is to show all of the components that will be assembled onto it’s two outer surfaces. The Assembly Drawing will be a guide for both the placement programmers and...
Whiteboard Wednesday: Team Collaboration
Communication and collaboration during a project are vital to ensure your design is completed on-time, on-budget and as smoothly as possible. There are many aspects to manage in a design and many...
Whiteboard Wednesday: Fabrication Drawings
The fabrication drawing will help the manufacturer produce your design accurately. Including the correct information in your fabrication drawing will streamline manufacturing by minimizing...
Signal Integrity Analysis of Serial Data Channels
Overview of BER analysis for DDR4 Interfaces with SystemSI.
DFM: Integrated Manufacturing Constraints
Manufacturing rules are managed as constraints in the familiar constraints manager, coexisting independently with electrical rules which can have more or less constrictive constraints.
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An demonstration of BER analysis for DDR4 Interfaces with SystemsSI.
Allegro FPGA System Planner: Managing architectural changes with Allegro FPGA System Planner
Learn how to manage architectural changes with Allegro FPGA System Planner.
Allegro FPGA System Planner: Create optimum pin assignments for FPGAs on PCBs
How to create optimum pin assignments for FPGAs on PCBs.
Allegro FPGA System Planner: Using patented pin assignment synthesis technology PART 2
Learn how Cadence's FPGA System planner can reduce your FPGA-based system design cycles.
Allegro FPGA System Planner: Using patented pin assignment synthesis technology PART 1
Learn how Cadence's FPGA System planner can reduce your FPGA-based system design cycles.
Allegro Auto-Interactive Breakout Technology AiBT (no sound)
An overview of the Allegro auto-interactive breakout technology.
Dynamic Unused Pad Suppression
A quick demonstration of dynamic unused pad suppression inside of Allegro PCB Editor.
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Tutorial Cadence Auto-Interactive Convert Corner
An overview of the Cadence Auto-interactive convert corner feature.
Tutorial OrCAD Allegro Inter Layer Flex DRC
20-minute demo of the Cadence Allegro + PCB High Speed Option.
2X Productivity Gain Verifying DDR Controller Using Specman
Learn how Mike Bartley of Test and Verification Solutions helped their customer achieve a 2X productivity gain.
Ericsson Meets DDR and PCIE Specs While Avoiding Crosstalk